Senior Hardware FPGA Design Engineer(Dublin or Gdynia)
Benetel has been providing LTE Platforms for the Telecommunications market specifically targeting wireless infrastructure. Our leading edge modules are used by our clients in their Cellular Base Stations, predominantly small cells. The multi-disciplinary team members are experts in Wireless Standards, Embedded Software, DSP, RF Design, Digital, Mechanical and Test System design. In 2018, we have embarked on a strategic initiative to provide Remote Radio Units (RRU) for CloudRAN networks of the future.
Our internal capabilities cover all phases of product development from System Architecture, Design, and Conformance Testing to Automated Test Systems to support high volume product manufacturing. Our innovative product development approach has contributed several world firsts in low-power and cellular small cell product development. We work closely with major semiconductor and software companies and are committed to delivering the very latest technology products to our global customer base.
Benetel is currently recruiting a Senior Hardware Design Engineer with outstanding FPGA development skills who will be responsible for definition and architecture of leading edge board level Remote Radio Unit systems for our current and future small cell applications. The role spans the full development life-cycle through specification, design, documentation, implementation, debug and test. Position and salary are highly dependent on experience.
The established team working environment provides an opportunity to develop and grow skills and expertise in embedded system hardware development for leading edge wireless technologies.
The role can be based in either our headquarter in Dublin or our new development location in the Tricity metropolitan area in Poland.
Desired Skills and Expertise
Educational and Experience Requirements
A Bachelor’s Degree in Electronic or Computer Engineering or other relevant discipline and 5+ years of relevant experience is required. Position and salary highly dependent on experience.
It is expected that candidates will have demonstrated some or all of the following competencies.
- 5+ years of experience at system architect level for FPGA/ARM based designs.
- Systemization of a digital ASIC (FPGA, ARM, SoC).
- Knowledge of FPGA/ARM and IP Cores systemization.
- Understanding of hardware, firmware, and software/hardware interactions.
- Knowledge of multi-gigabit interface protocols (Ethernet, SGMII, RGMII), memory technologies (DDR3, DDR4), interconnect protocols (PCIe), digital logics and common communication interfaces (UART, USB, SPI, I2C) is highly desired.
- Experience in digital frontend design (DSP, CFR, DPD, Up and Down Converters, Digital Filters).
- Experience in SoC performance and power estimation and optimization, clock and reset distribution optimization.
- Work with internal and external partners to bring reference designs to production.
- Experience working with Xilinx Zynq-7000 and/or Intel Arria-V SoC is a plus.
- Knowledge of RF radio transceiver is a plus.
- Active collaboration with multidisciplinary team on architecture and design within digital design expertise. Provide inputs to architecture and design reviews.
- Ability to work effectively with multidisciplinary engineering team is a must.
- 5+ years hands-on Verliog and/or SystemVerilog experience.
- Experience with scripting languages such as Tcl or Python
- Experience with programming languages such as C/C++ including low-level programming (firmware) of complex computer systems and mixing HDL with C/C++ for simulation purpose.
- Strong knowledge of FPGA tool flows; Synthesis, Partitioning, Place & Route: Xilinx Vivado HLx and Intel FPGA Quartus Prime Standard/Pro Edition.
- Be familiar with software development process: source version control tools (Git), unit tests (TDD), code review, refactoring, automate builds (CMake), continuous integration (CI) and continuous deployment (CD).
- Experience in logic synthesis, verification, timing closure, and physical design principles.
- Experience with highly pipelined designs, and with multiple-clock-domain designs
- Knowledge of SystemC (IEEE 1666-2011), UVM (IEEE 1800.2-2017) and/or SystemC-AMS (IEEE 1666.1-2016) is a plus